Design and Implementation of BRAM Memory for Reconfigurable Applications

Abstract

To improve device performance, reconfigurable computing refers to including application-specific hardware in accordance with various applications. Dynamic reconfiguration allows a portion of the hardware to be modified by the device while the rest remains operational. Furthermore, the FPGA configuration registers access by an internal configuration access port(ICAP). By specializing in the machine for a particular application, reconfigurable computing increases system performance. Application reconfiguration can only increase the performance of the system if the time complexity exceeds the initialization period. This ensures that only the device efficiency of quasi-static applications can be enhanced by dynamic reconfiguration. Typical reconfiguration times were obtained in milliseconds and this still holds for most applications, despite ongoing study. This is because of their long period or the delay generated by the process of reconfiguration. Different attempts have been made to increase the system's throughput to rival that of the ICAP controller to overcome these drawbacks and migrate reconfigurable computing to complex applications. Reconfiguration may increase the utilization of the region as well. To demonstrate the feasibility of the proposed BRAM-based architectural design for the reconfiguration of real-time applications and to check the literature's proposed throughput is the only aim of this project.