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A Wallace tree technique using Modified Unsigned Multiplier is proposed in this paper and is designed at gate level using Verilog HDL. Synthesized for Xilinx Virtex 6 low power, Spartan 6, Spartan 3E FPGA device. The result shows an improvement in terms of speed and slices or area. Performance and Area of integrated circuits are a major concern for VLSI circuit designers. This paper aims at more reduction of the latency and area or the number of slices. Day to day advent of new technology in the fields of digital signal processing and communication, VLSI, there is a great demand for the high-speed processing and Efficient area reduction in the design. Index Terms—Wallace tree Technique, Unsigned Multiplier, VLSI.
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