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In today’s Semiconductor Industry, at front-end level various IPs are designed separately and later to form a complex System on Chip, those are connected together to establish a proctocolitis communication. For such connection to form between various IPs, it becomes essential to design a interconnect which will follow all protocol rules and establish a correct information bypass. Advanced eXtensible Interface is such a type of protocol for microcontroller SoCs, primarily falling under AMBA family of ARM Holdings. All the data, address and response channels included in AXI are separate and independent. Once such a protocol design is done, there is extensive need of its verification by testing it in all the possible scenarios. The interconnect is quite crucial component when multiple masters and multiple slaves are used in a design environment. Interconnect makes sure that all the data coming from any of the masters is properly routed to the destined slave. The paper discusses about design of such a AMBA AXI4 based Interconnect UVC component which is used to verify a designed interconnect by giving various test scenarios alongside a multiple master and multiple slave environment.
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